Simulator Path
/<simulator install path>/bin (Linux*)
3. On the Assignments menu, click Settings.
4. In the Category list, under EDA Tool Settings select Simulation.
5. In the Tool name list, select your simulator.
Note: ModelSim refers to ModelSim SE and PE. These simulators use the same
commands as QuestaSim.ModelSim - Intel FPGA Edition refers to ModelSim - Intel
FPGA Edition Starter Edition and ModelSim - Intel FPGA Edition Subscription
Edition.
6. In the Output directory, browse to the directory for your output files.
7. To map illegal HDL characters, turn on Map illegal HDL characters.
8. To filter netlist glitches , turn on Enable glitch filtering.
9. Complete the following steps to specify additional options for NativeLink
automation:
a. Turn on Compile test bench.
b. Click Test Benches.
The Test Benches dialog box appears.
c. Click New.
d. Under Create new test bench settings, for Test bench name type the test
bench name. For Top level module in the test bench, type the top-level module
name. These names should match the actual test bench module names.
e. Select Use test bench to perform VHDL timing simulation and specify the
name of your design instance under Design instance name in test bench.
f. Under the Simulation period, turn on Run simulation until all vector
stimuli are used.
g. Under Test bench and simulation files, select your test bench file from your
folder. Click Add.
h. Click OK.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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