Intel Arria 10 User Manual

Protocol Transceiver PHY IP
Core
PCS Support Transceiver
Configuration Rule
(9)
Protocol Preset
(10)
1000BASE-X Gigabit
Ethernet
Native PHY IP core Standard GbE GIGE - 1.25 Gbps
1000BASE-X Gigabit
Ethernet with 1588
Native PHY IP core Standard GbE 1588 GIGE - 1.25 Gbps
1588
10GBASE-R Native PHY IP core Enhanced 10GBASE-R 10GBASE-R Low
Latency
10GBASE-R 1588 Native PHY IP core Enhanced 10GBASE-R 1588 10GBASE-R 1588
10GBASE-R with KR
FEC
Native PHY IP core Enhanced 10GBASE-R w/KR FEC 10GBASE-R w/KR FEC
10GBASE-KR and
1000BASE-X
1G/10GbE and
10GBASE-KR PHY
IP
(12)
Standard and
Enhanced
Not applicable BackPlane_wo_1588
LineSide (optical)
LineSide(optical)_158
8
40GBASE-R Native PHY IP core Enhanced Basic (Enhanced PCS) Low Latency Enhanced
PCS
(13)
40GBASE-R with FEC/
40GBASE-KR4
(14)
Native PHY IP core Enhanced Basic w/KR FEC User created
100GBASE-R via
CAUI-4/CPPI-4/BP and
CEI-25G
Native PHY IP core Enhanced and PCS
Direct
Basic (Enhanced
PCS) / PCS Direct
Low Latency GT
(15)
100GBASE-R via CAUI Native PHY IP core Enhanced Basic (Enhanced PCS) Low Latency Enhanced
PCS
(16)
100GBASE-R via CAUI
with FEC
Native PHY IP core Enhanced Basic w/KR FEC User created
XAUI XAUI PHY IP core Soft PCS Not applicable Not applicable
SPAUI Native PHY IP core Standard and
Enhanced
Basic/Custom
(Standard PCS)
User created
continued...
(9)
For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10)
For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(12)
The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training,
auto speed negotiation, and sequencer functions.
(13)
To implement 40GBASE-R using the Low Latency Enhanced PCS preset, change the number of
data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(14)
Link training, auto speed negotiation and sequencer functions are not included in the Native
PHY IP. The user would have to create soft logic to implement these functions when using
Native PHY IP.
(15)
Low Latency GT protocol preset requires some modification to implement CAUI-4/CPPI-4/BP-4
and CEI-25G.
(16)
To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the
number of data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
42

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex