Intel Arria 10 User Manual

Protocol Transceiver PHY IP
Core
PCS Support Transceiver
Configuration Rule
(9)
Protocol Preset
(10)
Basic (Enhanced PCS)
DDR XAUI Native PHY IP core Standard and
Enhanced
Basic/Custom
(Standard PCS)
Basic (Enhanced PCS)
User created
Interlaken (CEI-6G/
11G)
(17)
Native PHY IP core Enhanced Interlaken Interlaken
10x12.5Gbps
Interlaken
6x10.3Gbps
Interlaken
1x6.25Gbps
OTU-4 (100G) via
OTL4.10/OIF SFI-S
Native PHY IP core Enhanced Basic (Enhanced PCS) SFI-S 64:64 4x11.3
Gbps
(18)
OTU-3 (40G) via
OTL3.4/OIF SFI-5.2/
SFI-5.1
Native PHY IP core Enhanced Basic (Enhanced PCS) User created
OTU-2 (10G) via SFP
+/SFF-8431/CEI-11G
Native PHY IP core Enhanced Basic (Enhanced PCS) User created
OTU-2 (10G) via OIF
SFI-5.1s
Native PHY IP core Enhanced Basic (Enhanced PCS) User created
OTU-1 (2.7G) Native PHY IP core Standard Basic/Custom
(Standard PCS)
User created
SONET/SDH STS-768/
STM-256 (40G) via
OIF SFI-5.2/STL256.4
Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SONET/SDH STS-768/
STM-256 (40G) via
OIF SFI-5.1
Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SONET/SDH STS-192/
STM-64 (10G) via SFP
+/SFF-8431/CEI-11G
Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SONET/SDH STS-192/
STM-64 (10G) via OIF
SFI-5.1s/SxI-5/
SFI-4.2
Native PHY IP core Enhanced Basic (Enhanced PCS) User created
SONET STS-96 (5G)
via OIF SFI-5.1s
Native PHY IP core Enhanced Basic/Custom
(Standard PCS)
SONET/SDH OC-96
continued...
(9)
For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10)
For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(17)
A Transmit PCS soft bonding logic required for multi-lane bonding configuration is provided in
the design example.
(18)
To implement OTU-4 (100G) via OTL4.10/OIF SFI-S using SFI-S 64:64 4x11.3Gbps preset,
change the number of data channels to 10 for OTL4.10 or user desired number of channels
and datarate implemented for SFI-S.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
43

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English