Intel Arria 10 User Manual

Example 2:
Switching from pll_refclk2 to pll_refclk3, you need to read-modify-write to
both fPLL refclk selection MUX_0 and MUX_1:
1. Modify MUX_0 value:
• Read from 0x11A [7:0]
• Write the value read from 0x11A [7:0] to 0x114 [7:0]
2. Modify MUX_1 value:
• Read from 0x120 [7:0]
• Write the value read from 0x120 [7:0] to 0x11C [7:0]
Related Information
Steps to Perform Dynamic Reconfiguration on page 516
6.11.2.3. CDR and CMU Reference Clock Switching
You can use the reconfiguration interface to specify which reference clock source
drives the CDR and CMU PLL. The CDR and CMU support clocking by up to five
different reference clock sources.
Before initiating a reference clock switch, ensure that your CDR and CMU defines more
than one reference clock source. For the CDR, specify the parameter on the RX PMA
tab during the Native PHY IP parameterization. For the CMU, specify the Number of
PLL reference clocks under the PLL tab when parameterizing the CMU PLL.
The following table describes the addresses and bits for switching CDR and CMU
reference clock inputs. The number of exposed rx_cdr_refclk (CDR) or
pll_refclk (CMU) varies according to the number of reference clocks you specify.
Use the CMU reconfiguration interface for switching the CMU reference clock.
Table 271. Register Map for Switching CDR Reference Clock Inputs
Native PHY Port Description Address Bits
cdr_refclk0 Represents logical refclk0.
Lookup register x16A[7:0]
stores the mapping from logical
refclk0 to the physical refclk.
0x16A (Lookup Register) [7:0]
cdr_refclk1 Represents logical refclk1.
Lookup register x16B[7:0]
stores the mapping from logical
refclk1 to the physical refclk.
0x16B (Lookup Register) [7:0]
cdr_refclk2 Represents logical refclk2.
Lookup register x16C[7:0]
stores the mapping from logical
refclk2 to the physical refclk.
0x16C (Lookup Register) [7:0]
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex