Intel Arria 10 User Manual

Transceiver fPLL Port Description Address Bits
N/A
fPLL refclk selection MUX_0.
0x114 [7:0]
pll_refclk0 Represents logical refclk0 for MUX_1. Lookup
register x11D[7:0] stores the mapping from logical
refclk0 to the physical refclk for MUX_1.
0x11D (Lookup Register) [7:0]
pll_refclk1 Represents logical refclk1 for MUX_1. Lookup
register x11E[7:0] stores the mapping from logical
refclk1 to the physical refclk for MUX_1.
0x11E (Lookup Register) [7:0]
pll_refclk2 Represents logical refclk2 for MUX_1. Lookup
register x11F[7:0] stores the mapping from logical
refclk2 to the physical refclk for MUX_1.
0x11F (Lookup Register) [7:0]
pll_refclk3 Represents logical refclk3 for MUX_1. Lookup
register x120[7:0] stores the mapping from logical
refclk3 to the physical refclk for MUX_1.
0x120 (Lookup Register) [7:0]
pll_refclk4 Represents logical refclk4 for MUX_1. Lookup
register x121[7:0] stores the mapping from logical
refclk4 to the physical refclk for MUX_1.
0x121 (Lookup Register) [7:0]
N/A
fPLL refclk selection MUX_1.
0x11C [7:0]
Specify the logical reference clock and respective address and bits of the replacement
clock when performing a reference clock switch. Follow this procedure to switch to the
selected reference clock:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the lookup register for MUX 0 and save the required 8-bit pattern. For
example, switching to logical refclk3 requires use of bits[7:0] at lookup register
0x11A.
3. Perform a read-modify-write to bits [7:0] at address 0x114 using the 8-bit value
obtained from the lookup register.
4. Read from the lookup register for MUX 1 and save the required 8-bit pattern. For
example, switching to logical refclk3 requires use of bits[7:0] at lookup register
0x120.
5. Perform a read-modify-write to bits [7:0] at address 0x11C using the 8-bit value
obtained from the lookup register.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Example 1:
Switching from pll_refclk0 to pll_refclk1, you need to read-modify-write to
both fPLL refclk selection MUX_0 and MUX_1:
1. Modify MUX_0 value:
• Read from 0x118[7:0]
• Write the value from 0x118 [7:0] to 0x114 [7:0]
2. Modify MUX_1 value:
• Read from 0x11E [7:0]
• Write the value read from 0x11E [7:0] to 0x11C [7:0]
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex