Intel Arria 10 User Manual

The Backplane Ethernet 10GBASE-KR PHY IP core includes the following new modules
to enable operation over a backplane:
• Link Training (LT)— The LT mechanism allows the 10GBASE-KR PHY to
automatically configure the link-partner TX PMDs for the lowest Bit Error Rate
(BER). LT is defined in Clause 72 of IEEE Std 802.3ap-2007.
• Auto negotiation (AN)—The 10GBASE-KR PHY IP core can auto-negotiate between
1000BASE-KX (1GbE) and 10GBASE-KR (10GbE) PHY types. The AN function is
mandatory for Backplane Ethernet. It is defined in Clause 73 of the IEEE Std
802.3ap-2007.
• Forward Error Correction (FEC)—FEC function is an optional feature defined in
Clause 74 of IEEE 802.3ap-2007. It provides an error detection and correction
mechanism.
Related Information
• IEEE Std 802.3ap-2008 Standard
• Standard for a Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems
2.6.3.1. 10GBASE-KR PHY Release Information
Table 106. 10GBASE-KR PHY Release Information
Item Description
Version 16.0
Release Date May 2016
Ordering Codes IP-10GBASEKRPHY (IP)
IPR-10GBASEKRPHY (Renewal)
Product ID 0106
Vendor ID 6AF7
2.6.3.2. 10GBASE-KR PHY Performance and Resource Utilization
This topic provides performance and resource utilization for the IP.
The following table shows the typical expected resource utilization for selected
configurations using the Quartus Prime software v15.1 for Arria 10 devices. The
numbers of ALMs and logic registers are rounded up to the nearest 100.
Table 107. 10GBASE-KR PHY Performance and Resource Utilization
Variant ALMs ALUTs Registers M20K
10GBASE-KR PHY 2400 3750 3100 1
10GBASE-KR PHY with FEC 2400 3750 3100 1
2.6.3.3. 10GBASE-KR Functional Description
The following figure shows the supporting components inside the 10GBASE-KR PHY IP
core.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex