Intel Arria 10 User Manual

Figure 68. 10GBASE-KR PHY IP Core Block Diagram
Registers
GbE
PCS
1588
FIFO
Auto-Negotiation
Clause 73
Link Training
Clause 72
HSSI Reconfiguration
Requests
1588
FIFO
GbE
PCS
Native PHY
Standard RX PCS
TX PMA
RX PMA
40/32
40/32
rx_pld_clk rx_pma_clk
Standard TX PCS
tx_pld_clk tx_pma_clk
Enhanced TX PCS
tx_pld_clk tx_pma_clk
Enhanced RX PCS
rx_pld_clk rx_pma_clk
Divide by 33/1/2
Avalon-MM
8 + 2
64 + 8
TX_GMII_DATA
XGMII_TX_CLK
TX_XGMII_DATA
TX_PMA_CLKOUT
RX_XGMII_DATA
64 + 8
8 + 2
XGMII_RX_CLK
RX_GMII_DATA
32
64 + 8
Soft Logic Hard Logic
Register
Access
Nios II LT Interface
64 + 8
Nios II Sequencer
Interface
10GBASE-KR PHY IP
Unused
Note: The 10GBASE-KR PHY IP core does not support backplane applications with IEEE 1588
Precision Time Protocol.
The 10GBASE-KR PHY IP core includes the following components:
Standard and Enhanced PCS Datapaths
The Enhanced PCS and PMA inside the Native PHY are configured to be the 10GBASE-
R PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters for more
details on how these blocks support 1G, 10G protocols and FEC.
Auto Negotiation, IEEE 802.3 Clause 73
The auto negotiation (AN) is needed to synchronize the start time of the link training
on both sides of the link partners. This ensures that the link training can be done
effectively within the 500 ms of the specified time frame as required.
Link Training (LT), IEEE 802.3 Clause 72
Arria 10 devices have soft link training IP that complies with the IEEE 802.3 Clause 72
standard training procedure. This IP includes:
• training frame lock that is different from the regular 64b/66b frame_lock
• training frame generation
• the control channel codec
• Local Device (LD) coefficient update
• Link Partner (LP) coefficient generation
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
137

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex