Intel Arria 10 User Manual

Figure 255. 8B/10B Encoder Block Diagrams
8B/10B Encoderdataout[9:0]
To the Serializer
datain[7:0]
tx_datak
tx_forcedisp
tx_dispval
From the Byte Serializer
When the PCS-PMA Interface Width is 10 bits
8B/10B Encoder
dataout[19:10]
To the Serializer
datain[15:8]
tx_datak[1]
tx_forcedisp[1]
tx_dispval[1]
From the Byte Serializer
dataout[9:0]
datain[7:0]
tx_datak[0]
tx_forcedisp[0]
tx_dispval[0]
MSB
Encoding
LSB
Encoding
When the PCS-PMA Interface Width is 20 bits
When the PCS-PMA interface width is 10 bits, one 8B/10B encoder is used to convert
the 8-bit data into a 10-bit output. When the PCS-PMA interface width is 20 bits, two
cascaded 8B/10B encoders are used to convert the 16-bit data into a 20-bit output.
The first eight bits (LSByte) is encoded by the first 8B/10B encoder and the next eight
bits (MSByte) is encoded by the second 8B/10B encoder. The running disparity of the
LSByte is calculated first and passed on to the second encoder to calculate the running
disparity of the MSByte.
Note: You cannot enable the 8B/10B encoder when the PCS-PMA interface width is 8 bits or
16 bits.
5.3.1.3.1. 8B/10B Encoder Control Code Encoding
Figure 256. Control Code Encoding Diagram
tx_clkout
8378 BCBC 0F00 BF3C
0 1 0
D3.4 D24.3 D28.5 K28.5 D15.0 D0.0 D31.5 D28.1
tx_parallel_data[15:0]
tx_datak[1:0]
Code Group
The tx_datak signal indicates whether the 8-bit data being sent at the
tx_parallel_data port should be a control word or a data word. When tx_datak
is high, the 8-bit data is encoded as a control word (Kx.y). When tx_datak is low,
the 8-bit data is encoded as a data word (Dx.y). Depending upon the PCS-PMA
interface width, the width of tx_datak is either 1 bit or 2 bits. When the PCS-PMA
interface width is 10 bits, tx_datak is a 1-bit word. When the PCS-PMA interface
width is 20 bits, tx_datak is a 2-bit word. The LSB of tx_datak corresponds to the
LSByte of the input data sent to the 8B/10B encoder and the MSB corresponds to the
MSByte of the input data sent to the 8B/10B encoder.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
483

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex