Intel Arria 10 User Manual

Document
Version
Changes
• Updated the switching bit register definitions in the “Register Map for Switching fPLL Reference
Clock Inputs” table
• Updated the “Bit Values to Be Set” table in the “Enabling and Disabling Loopback Modes Using
Direct Reconfiguration Flow” section.
2015.11.02 Made the following changes:
• Changed the procedure in the "Steps to Perform Dynamic Reconfiguration" section to be more
general, allowing procedures in other sections to refer to it.
• Added the "Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow" section.
• Added the "Analog PMA Settings (Optional) for Dynamic Reconfiguration" table.
• Removed four tables from the "On-Die Instrumentation" section.
• Changed the procedure in the "Using ODI to Build On-chip Eye Process" section.
• Added entry to “Arria 10 Dynamic Reconfiguration Feature Support” table
• Improved description of access requests in the “Interacting with the Reconfiguration Interface”
section
• Updated the “Configuration Files” section
• Added information to the “Embedded Reconfiguration Streamer” section
• Modified the “Arria 10 Native PHY with Embedded Streamer” figure
• Described the two levels of arbitration in the “Arbitration” section
• Converted the “Steps to Perform Dynamic Reconfiguration” figure in the “Steps to Perform Dynamic
Reconfiguration” section to a set of procedures
• Added the “Reset Recommendations for Dynamic Reconfiguration” section
• Added information about the PMA analog settings to the “Changing PMA Analog Parameters” section
• Added steps to the procedure in the “Changing CTLE Settings in Manual Mode” section
• Updated the steps in the procedures in the “Serial Loopback Mode” section
• Changed title of “IP Guided Reconfiguration Flow” to “Native PHY or PLL IP Guided Reconfiguration
Flow”
• Updated the steps in the procedures in the “Native PHY or PLL IP Guided Reconfiguration Flow” and
added a note following the first procedure
• Updated the steps in the procedure in the “Switching Transmitter PLL” section
• Updated the steps in the procedures in the “ATX Reference Clock,” “fPLL Reference Clock,” and “CDR
and CMU Reference Clock,” sections
• Updated the “Avalon Interface Parameters” table to show which parameter editors are valid for each
parameter
• Corrected values in step 1a in the “Start Pattern Checker” section
• Added information about hard PRBS blocks to the “PRBS Soft Accumulators” section
• Added list of PRBS checker control and status signals to the “Using PRBS and Square Wave Data
Pattern Generator and Checker” section
• Updated the steps in the procedures in the “Enabling the PRBS and Square Wave Data Generator”
and the “Enabling the PRBS and Data Checker” sections
• Updated the steps in the procedures in the “Examples of Enabling the PRBS9 and PRBS31 Pattern
Generators” and the “Examples of Enabling the PRBS Data Checker” sections
• Updated the steps in the procedure in the “Enabling Pseudo Random Pattern Mode” section
2015.05.11
Made the following changes:
• Completely revised, updated, and reorganized the chapter.
• Added the following new sections:
— Multiple Reconfiguration Profiles
— Embedded Reconfiguration Streamer
— Arbitration
— Enabling and Disabling Loopback Modes
— IP Guided Reconfiguration Flow
— On-Die Instrumentation
— Altera Debug Master Endpoint
— ODI Acceleration Logic
2014.12.15 Made the following changes:
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
565

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex