Intel Arria 10 User Manual

Word
Addr
Bit R/W Name Description
3 RO
Link Training
failure
When set to 1, a training failure has been detected. When set to
0, a training failure has not been detected. For more information,
refer to the state variable training_failure as defined in Clause
72.6.10.3.1 and bit 10GBASE_KR PMD status register bit
(1.151.3) of IEEE 802.3ap-2007.
4 RO
Link Training Error
When set to 1, excessive errors occurred during Link Training.
When set to 0, the BER is acceptable.
5 RO
Link Training Frame
lock Error
When set to 1, indicates a frame lock was lost during Link
Training. If the tap settings specified by the fields of 0x4D5 are
the same as the initial parameter value, the frame lock error was
unrecoverable.
6 RO
RXEQ Frame Lock
Loss
Frame lock not detected at some point during RXEQ, possibly
triggering conditional RXEQ mode.
7 RO
CTLE Fine-grained
Tuning Error
Could not determine the best CTLE due to maximum BER limit at
each step in the fine-grained tuning mode.
0x4D3 9:0 RW
ber_time_frames
Specifies the number of training frames to examine for bit errors
on the link for each step of the equalization settings. Used only
when ber_time_k_frames is 0. The following values are
defined:
• A value of 2 is about 10
3
bytes
• A value of 20 is about 10
4
bytes
• A value of 200 is about 10
5
bytes
The default value for simulation is 2'b11. The default value for
hardware is 0.
19:10 RW
ber_time_k_frames
Specifies the number of thousands of training frames to examine
for bit errors on the link for each step of the equalization settings.
Set ber_time_m_frames = 0 for time/bits to match the
following values:
• A value of 3 is about 10
7
bits = About 1.3 ms
• A value of 25 is about 10
8
bits = About 11 ms
• A value of 250 is about 10
9
bits = About 110 ms
The default value for simulation is 0. The default value for
hardware is 0x415.
29:20 RW
ber_time_m_frames
Specifies the number of millions of training frames to examine for
bit errors on the link for each step of the equalization settings.
Set ber_time_k_frames = 4'd1000 = 0x43E8 for time/bits to
match the following values:
• A value of 3 is about 10
10
bits = About 1.3 seconds
• A value of 25 is about 10
11
bits = About 11 seconds
• A value of 250 is about 10
12
bits = About 110 seconds
0x4D4 5:0 RO or
RW
LD coefficient
update[5:0]
Reflects the contents of the first 16-bit word of the training frame
sent from the local device control channel. Normally, the bits in
this register are read-only; however, when you override training
by setting the Ovride Coef enable control bit, these bits
become writable. The following fields are defined:
• [5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as [5:4])
• [1:0]: Coefficient (-1) update (same encoding as [5:4])
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
188

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex