Intel Arria 10 User Manual

Word
Addr
Bit R/W Name Description
The default value is 010.
15 RW
disable Initialize
PMA on
max_wait_timeout
When set to 1, PMA values (VOD, pre-tap, post-tap) are not
initialized upon entry into the Training_Failure state. This
happens when max_wait_timer_done, which sets
training_failure = true (reg 0x4D2 bit 3). Used for
University of New Hampshire (UNH) testing. When set to 0, PMA
values are initialized upon entry into Training_Failure state.
Refer to Figure 72-5 of IEEE 802.3ap-2007 for more details.
16 RW
Ovride LP Coef
enable
When set to 1, overrides the link partner's equalization
coefficients; software changes the update commands sent to the
link partner TX equalizer coefficients. When set to 0, uses the Link
Training logic to determine the link partner coefficients. Used with
0x4D1 bit-4 and 0x4D4 bits[7:0].
17 RW
Ovride Local RX
Coef enable
When set to 1, overrides the local device equalization coefficients
generation protocol. When set, the software changes the local TX
equalizer coefficients. When set to 0, uses the update command
received from the link partner to determine local device
coefficients. Used with 0x4D1 bit-8 and 0x4D4 bits[23:16]. The
default value is 1.
0x4D0 22 RW
adp_ctle_mode
Reserved. Default = 000
28:24 RW
Manual ctle
Reserved
31:29 RW
max_post_step[2:0]
Reserved
0x4D1 0 RW
Restart Link
training
When set to 1, resets the 10GBASE-KR start-up protocol. When
set to 0, continues normal operation. This bit self clears. For more
information, refer to the state variable mr_restart_training as
defined in Clause 72.6.10.3.1 and 10GBASE-KR PMD control
register bit (1.150.0) IEEE 802.3ap-2007.
4 RW
Updated TX Coef new
When set to 1, there are new link partner coefficients available to
send. The LT logic starts sending the new values set in 0x4D4
bits[7:0] to the remote device. When set to 0, continues normal
operation. This bit self clears. Must enable this override in 0x4D0
bit 16.
8 RW
Updated RX coef new
When set to 1, new local device coefficients are available. The LT
logic changes the local TX equalizer coefficients as specified in
0x4D4 bits[23:16]. When set to 0, continues normal operation.
This bit self clears. Must enable the override in 0x4D0 bit17.
0x4D2 0 RO
Link Trained -
Receiver status
When set to 1, the receiver is trained and is ready to receive
data. When set to 0, receiver training is in progress. For more
information, refer to the state variable rx_trained as defined in
Clause 72.6.10.3.1 and bit 10GBASE-KR PMD control register bit
10GBASE_KR PMD status register bit (1.151.0) of IEEE
802.3ap-2007.
1 RO
Link Training Frame
lock
When set to 1, the training frame delineation has been detected.
When set to 0, the training frame delineation has not been
detected. For more information, refer to the state variable
frame_lock as defined in Clause 72.6.10.3.1 and 10GBASE_KR
PMD status register bit 10GBASE_KR PMD status register bit
(1.151.1) of IEEE 802.3ap-2007.
2 RO
Link Training
Start-up protocol
status
When set to 1, the start-up protocol is in progress. When set to 0,
start-up protocol has completed. For more information, refer to
the state training as defined in Clause 72.6.10.3.1 and
10GBASE_KR PMD status register bit (1.151.2) of IEEE
802.3ap-2007.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
187

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex