Intel Arria 10 User Manual

Word
Addr
Bit R/W Name Description
• A0 1000BASE-KX
• A1 10GBASE-KX4
• A2 10GBASE-KR
• A3 40GBASE-KR4
• A4 40GBASE-CR4
• A5 100GBASE-CR10
• A24:6 are reserved
For more information, refer to Clause 73.6.4 and AN LP base page
ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap-2007.
26:25 RO
AN LP ADV
FEC_F[1:0]
Received FEC ability bits (F0:F1) is encoded in bits D46:D47 of
the base Link Codeword. F0 is FEC ability. F1 is FEC requested.
See Clause 73.6.5 of IEEE 802.3ap-2007 for details.
27 RO
AN LP ADV Remote
Fault
Received Remote Fault (RF) ability bits. RF is encoded in bit D13
of the base link codeword in Clause 73 AN. For more information,
refer to Clause 73.6.7 and bits AN LP base page ability register
AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE
802.3ap-2007.
30:28 RO
AN LP ADV Pause
Ability_C[2:0]
Received pause ability bits. Pause (C0:C1) is encoded in bits
D11:D10 of the base link codeword in Clause 73 AN as follows:
• C0 is the same as PAUSE as defined in Annex 28B
• C1 is the same as ASM_DIR as defined in Annex 28B
• C2 is reserved
For more information, refer to bits AN LP base page ability
registers (7.19-7.21) of Clause 45 of IEEE 802.3ap-2007.
0x4D0 0 RW
Link Training
enable
When 1, enables the 10GBASE-KR start-up protocol. When 0,
disables the 10GBASE-KR start-up protocol. The default value is
1. For more information, refer to Clause 72.6.10.3.1 and
10GBASE-KR PMD control register bit (1.150.1) of IEEE
802.3ap-2007.
1 RW
dis_max_wait_tmr When set to 1, disables the LT max_wait_timer . Used for
characterization mode when setting much longer bit error rate
(BER) timer values.
2 RW
quick_mode
When set to 1, only the init and preset values calculate the best
BER.
3 RW
pass_one
When set to 1, the BER algorithm considers more than the first
local minimum when searching for the lowest BER. The default
value is 1.
7:4 RW
main_step_cnt [3:0]
Specifies the number of equalization steps for each main tap
update. There are about 20 settings for the internal algorithm to
test. The valid range is 1-15. The default value is 4'b0010.
11:8 RW
prpo_step_cnt [3:0]
Specifies the number of equalization steps for each pre- and post-
tap update. From 16-31 steps are possible. The default value is
4'b0001.
0x4D0 14:12 RW
equal_cnt [2:0]
Adds hysteresis to the error count to avoid local minimums. The
following values are defined:
• 000 = 0
• 001 = 1
• 010 = 2
• 011 = 3
• 100 = 4
• 101 = 8
• 110 = 16
• 111 = Reserved
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
186

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex