Intel Arria 10 User Manual

Figure 131. Transceiver Channel Datapath and Clocking for Basic Configuration with Low
Latency Enabled
The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width
is 10 bits.
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
/2
/2
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Clock Divider
rx_pma_div_clkout
Serial Clock
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
tx_coreclkin
rx_coreclkin
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider)
PRBS
Verifier
tx_pma_div_clkout
10
10
16
16
62.5 MHz (1)
62.5 MHz (1)
Notes:
1. The parallel clock (tx_clkout or rx_clkout) is calculated as data rate/PCS-PMA interface width = 1250/10 = 125 MHz.
When the Byte Serializer is set to Serialize x2 mode, tx_clkout and rx_clkout become 1250/20 = 62.5 MHz.
2. The serial clock is calculated as data rate/2. The PMA runs on a dual data rate clock.
tx_clkout
rx_clkout
tx_clkout
125 MHz (1)
125 MHz (1)
rx_clkout or
tx_clkout
tx_clkout
625 MHz (2)
In low latency modes, the transmitter and receiver FIFOs are always enabled.
Depending on the targeted data rate, you can optionally bypass the byte serializer and
deserializer blocks.
Related Information
Arria 10 Standard PCS Architecture on page 479
2.9.2.1. Word Aligner Manual Mode
To use this mode:
1. Set the RX word aligner mode to Manual (FPGA Fabric controlled).
2. Set the RX word aligner pattern length option according to the PCS-PMA
interface width.
3. Enter a hexadecimal value in the RX word aligner pattern (hex) field.
This mode adds rx_patterndetect and rx_syncstatus. You can select the
Enable rx_std_wa_patternalign port option to enable
rx_std_wa_patternalign. An active high on rx_std_wa_patternalign re-aligns
the word aligner one time.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
301

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex