Intel Arria 10 User Manual

2.9.2.14. TX Bit Reversal
The TX bit reversal feature can be enabled in low latency, basic, and basic rate match
mode. The word aligner is available in any mode. This feature is parameter-based, and
creates no additional ports. If there is more than one channel in the design, all
channels have TX bit reversal.
To enable TX bit reversal, select the Enable TX bit reversal option in Platform
Designer (Standard). It can also be dynamically controlled with dynamic
reconfiguration.
Figure 157. TX Bit Reversal
tx_parallel_data
rx_parallel_data
11111100001110111100
00000... 00111101110000111111
2.9.2.15. TX Byte Reversal
The TX byte reversal feature can be enabled in low latency, basic, and basic rate
match mode. The word aligner is available in any mode. This feature is parameter-
based, and creates no additional ports. If there is more than one channel in the
design, all channels have TX byte reversal.
To enable TX byte reversal, select the Enable TX byte reversal option in Platform
Designer (Standard). It can also be dynamically controlled with dynamic
reconfiguration.
Figure 158. TX Byte Reversal
tx_parallel_data
rx_parallel_data
11111100001110111100
00000000... 11101111001111110000
2.9.2.16. How to Implement the Basic, Basic with Rate Match Transceiver
Configuration Rules in Arria 10 Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture,
and the reset controller before implementing your Basic protocol IP.
1. Open the IP Catalog and select the Native PHY IP.
Refer to Select and Instantiate the PHY IP Core on page 33.
2. Select Basic/Custom (Standard PCS) or Basic/Custom w/Rate Match
(Standard PCS) from the Transceiver configuration rules list located under
Datapath Options depending on which configuration you want to use.
3. Use the parameter values in the tables in Transceiver Native PHY IP Parameter
Settings for the Basic Protocol as a starting point. Or, you can use the protocol
presets described in Transceiver Native PHY Presets. You can then modify the
setting to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex