Intel Arria 10 User Manual

Port Direction Clock Domain Description
tx_serial_clk_gt Output N/A High speed serial clock output port for
GT channels. Represents the GT clock
network.
pll_locked Output Asynchronous Active high status signal which
indicates if the PLL is locked.
pll_pcie_clk Output N/A Used for PCIe.
(54)
reconfig_clk0 Input N/A Optional Avalon interface clock. Used
for PLL reconfiguration. The
reconfiguration ports appear only if the
Enable Reconfiguration parameter is
selected in the PLL IP Core GUI. When
this parameter is not selected, the
ports are set to OFF internally.
reconfig_reset0 Input reconfig_clk0 Used to reset the Avalon interface.
Asynchronous to assertion and
synchronous to deassertion.
reconfig_write0 Input reconfig_clk0 Active high write enable signal.
reconfig_read0 Input reconfig_clk0 Active high read enable signal.
reconfig_address0[9:0] Input reconfig_clk0 10-bit address bus used to specify
address to be accessed for both read
and write operations.
reconfig_writedata0[31:0] Input reconfig_clk0 32-bit data bus. Carries the write data
to the specified address.
reconfig_readdata0[31:0] Output reconfig_clk0 32-bit data bus. Carries the read data
from the specified address.
reconfig_waitrequest0 Output reconfig_clk0 Indicates when the Avalon interface
signal is busy. When asserted, all
inputs must be held constant.
pll_cal_busy Output Asynchronous Status signal which is asserted high
when PLL calibration is in progress.
OR this signal with tx_cal_busy port
before connecting to the reset
controller IP.
mcgb_rst Input Asynchronous Master CGB reset control.
Deassert this reset at the same time as
pll_powerdown .
mcgb_aux_clk0 Input N/A Used for PCIe implementation to switch
between fPLL and ATX PLL during link
speed negotiation.
tx_bonding_clocks[5:0] Output N/A Optional 6-bit bus which carries the
low speed parallel clock outputs from
the master CGB. Each transceiver
channel in a bonded group has this 6-
bit bus.
Used for channel bonding, and
represents the x6/xN clock network.
mcgb_serial_clk Output N/A High speed serial clock output for
x6/xN non-bonded configurations.
continued...
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Connect this clock to hclk in PCIe applications.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
358

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex