Intel Arria 10 User Manual

Parameter Range Description
Generate SystemVerilog package
file
On/Off Generates a SystemVerilog package file containing all
relevant parameters used by the PLL.
Generate C header file On/Off Generates a C header file containing all relevant parameters
used by the PLL.
Enable multiple reconfiguration
profiles
On/Off Enables multiple configuration profiles to be stored.
Enable embedded reconfiguration
streamer
On/Off Enables embedded reconfiguration streamer which
automates the dynamic reconfiguration process between
multiple predefined configuration profiles.
Generate reduced reconfiguration
files
On/Off When enabled, the IP generates reconfiguration report files
containing only the setting differences between the multiple
reconfiguration profiles
Number of reconfiguration profiles 1 to 8 Specifies the number of reconfiguration profiles
Store current configuration to
profile
0 to 7 Specifies which configuration profile to modify (store, load,
clear or refresh) when clicking the corresponding action
button.
Generate MIF (Memory Initialize
File)
On/Off Generates a MIF file which contains the current
configuration.
Use this option for reconfiguration purposes in order to
switch between different PLL configurations.
Table 232. ATX PLL—Generation Options
Parameter Range Description
Generate parameter
documentation file
On/Off Generates a .csv file which contains descriptions of ATX PLL
IP core parameters and values.
Table 233. ATX PLL IP Core Ports
Port Direction Clock Domain Description
pll_powerdown Input Asynchronous Resets the PLL when asserted high.
Needs to be connected to a
dynamically controlled signal (the
Transceiver PHY Reset Controller
pll_powerdown output if using this
Intel FPGA IP).
pll_refclk0 Input N/A Reference clock input port 0.
There are a total of five reference clock
input ports. The number of reference
clock ports available depends on the
Number of PLL reference clocks
parameter.
pll_refclk1 Input N/A Reference clock input port 1.
pll_refclk2 Input N/A Reference clock input port 2.
pll_refclk3 Input N/A Reference clock input port 3.
pll_refclk4 Input N/A Reference clock input port 4.
tx_serial_clk Output N/A High speed serial clock output port for
GX channels. Represents the x1 clock
network.
continued...
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
357

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex