Intel Arria 10 User Manual

Parameter Range Description
This is used for x6/xN bonded and non-bonded modes.
Clock division factor 1, 2, 4, 8 Divides the master CGB clock input before generating
bonding clocks.
Enable x6/xN non-bonded high-
speed clock output port
On/Off Enables the master CGB serial clock output port used for
x6/xN non-bonded modes.
Enable PCIe clock switch interface On/Off Enables the control signals for the PCIe clock switch
circuitry. Used for PCIe clock rate switching.
Number of auxiliary MCGB clock
input ports
0, 1 Auxiliary input is used to implement the PCIe Gen3
protocol.
MCGB input clock frequency Read only Displays the master CGB's input clock frequency.
MCGB output data rate. Read only Displays the master CGB's output data rate.
Enable bonding clock output ports On/Off
Enables the tx_bonding_clocks output ports of the
master CGB used for channel bonding.
This option should be turned ON for bonded designs.
Enable feedback compensation
bonding
On/Off Enables this setting when using feedback compensation
bonding. For more details about feedback compensation
bonding, refer to the PLL Feedback Compensation Bonding
section later in the document.
PMA interface width 8, 10, 16, 20,
32, 40, 64
Specifies PMA-PCS interface width.
Match this value with the PMA interface width selected for
the Native PHY IP core. You must select a proper value for
generating bonding clocks for the Native PHY IP core.
Table 231. ATX PLL—Dynamic Reconfiguration
Parameter Range Description
Enable reconfiguration On/Off Enables the PLL reconfiguration interface. Enables the
simulation models and adds Avalon compliant ports for
reconfiguration.
Enable Altera Debug Master
Endpoint
On/Off When you turn on this option, the Transceiver PLL IP core
includes an embedded Altera Debug Master Endpoint
(ADME) that connects internally to the Avalon-MM slave
interface for dynamic reconfiguration. The ADME can access
the reconfiguration space of the transceiver. It can perform
certain test and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
Separate reconfig_waitrequest
from the status of AVMM
arbitration with PreSICE
On/Off
When enabled, the reconfig_waitrequest does not
indicate the status of AVMM arbitration with PreSICE. The
AVMM arbitration status is reflected in a soft status register
bit. (Only available if "Enable control and status registers
feature" is enabled).
Enable capability registers On/Off Enables capability registers that provide high-level
information about the ATX PLL's configuration.
Set user-defined IP identifier User-defined Sets a user-defined numeric identifier that can be read from
the user_identifier offset when the capability registers
are enabled.
Enable control and status registers On/Off Enables soft registers for reading status signals and writing
control signals on the PLL interface through the embedded
debug logic.
Configuration file prefix Enter the prefix name for the configuration files to be
generated.
continued...
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex