Intel Arria 10 User Manual

• If you use the ATX PLL, set the following configuration settings:
— Under the Master Clock Generation Block Tab
• Enable Include Master Clock Generation Block.
• Turn ON Enable Bonding Clock output ports.
• Turn ON Enable feedback compensation bonding.
— Under the Dynamic Reconfiguration Tab
• Turn ON Enable dynamic reconfiguration
• If you use the fPLL, set the following configuration settings:
— Under the PLL Tab
• Set the PLL Feedback type to feedback compensation bonding.
— Under the Master Clock Generation Block Tab
• Turn ON Enable Bonding Clock output ports.
— Under the Dynamic Reconfiguration Tab
• Turn ON Enable dynamic reconfiguration
3. Configure the Native PHY IP core using the IP Parameter Editor
• Set the Native PHY IP core TX Channel bonding mode to either PMA
bonding or PMA/PCS bonding.
• Turn ON Enable dynamic reconfiguration
4. Create a top level wrapper to connect the PLL IP cores to Native PHY IP core.
•
In this case, the PLL IP core has tx_bonding_clocks output bus with width
[5:0].
•
The Native PHY IP core has tx_bonding_clocks input bus with width [5:0]
multiplied by the number of channels in a transceiver bank. (six channels in
the transceiver bank).
• Unlike the x6/xN bonding mode, for this mode, the PLL should be instantiated
multiple times. (One PLL is required for each transceiver bank that is a part of
the bonded group.) Instantiate a PLL for each transceiver bank used.
•
Connect the tx_bonding_clocks output from each PLL to (up to) six
channels in the same transceiver bank.
• Connect the PLL IP core to the PHY IP core by duplicating the output of the
PLL[5:0] for the number of transceiver channels used in the bonding group.
Steps to recalibrate the PLL after power up calibration
1. Dynamic reconfigure the PLL to change the feedback from the master CGB to
feedback from PLL.
• For ATX PLL, Read-Modify-Write 0x1 to offset address 0x110[2] of the ATX
PLL.
• For fPLL, Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL.
2. Recalibrate the PLL.
3. After recalibration completes, ensure the PLL achieves lock. Dynamic reconfigure
the PLL to change the feedback to master CGB.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
407

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex