Intel Arria 10 User Manual

5.1.2.2.2. Lock-to-Data Mode
During normal operation, the CDR must be in LTD mode to recover the clock from the
incoming serial data. In LTD mode, the PD in the CDR tracks the incoming serial data
at the receiver input. Depending on the phase difference between the incoming data
and the CDR output clock, the PD controls the CDR charge pump that tunes the VCO.
Note:
The PFD is inactive in LTD mode. The rx_is_lockedtoref status signal toggles
randomly and is not significant in LTD mode.
After switching to LTD mode, the rx_is_lockedtodata status signal is asserted.
The actual lock time depends on the transition density of the incoming data and the
parts per million (ppm) difference between the receiver input reference clock and the
upstream transmitter reference clock. The rx_is_lockedtodata signal toggles until
the CDR sees valid data; therefore, you should hold receiver PCS logic in reset
(rx_digitalreset) for a minimum of 4 µs after rx_is_lockedtodata remains
continuously asserted.
5.1.2.2.3. CDR Lock Modes
You can configure the CDR in either automatic lock mode or manual lock mode. By
default, the Quartus Prime software configures the CDR in automatic lock mode.
Automatic Lock Mode
In automatic lock mode, the CDR initially locks to the input reference clock (LTR
mode). After the CDR locks to the input reference clock, the CDR locks to the
incoming serial data (LTD mode) when the following conditions are met:
• The signal threshold detection circuitry indicates the presence of valid signal levels
at the receiver input buffer when rx_std_signaldetect is enabled.
• The CDR output clock is within the configured ppm frequency threshold setting
with respect to the input reference clock (frequency locked).
• The CDR output clock and the input reference clock are phase matched within
approximately 0.08 unit interval (UI) (phase locked).
If the CDR does not stay locked to data because of frequency drift or severe amplitude
attenuation, the CDR switches back to LTR mode.
Manual Lock Mode
The PPM detector and phase relationship detector reaction times can be too long for
some applications that require faster CDR lock time. You can manually control the CDR
to reduce its lock time using two optional input ports (rx_set_locktoref and
rx_set_locktodata).
Table 253. Relationship Between Optional Input Ports and the CDR Lock Mode
rx_set_locktoref rx_set_locktodata
CDR Lock Mode
0 0 Automatic
1 0 Manual-RX CDR LTR
X 1 Manual-RX CDR LTD
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
459

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex