Intel Arria 10 User Manual

Most data transmission systems, such as Ethernet, have minimum requirements for
the bit error rate (BER). However, due to channel distortion or noise in the channel,
the required BER may not be achievable. In these cases, adding a forward error
control correction can improve the BER performance of the system.
The FEC sublayer is optional and can be bypassed. When used, it can provide
additional margin to allow for variations in manufacturing and environmental
conditions. FEC can achieve the following objectives:
• Support a forward error correction mechanism for the 10GBASE-R/KR and
40GBASE-R/KR protocols.
• Support the full duplex mode of operation of the Ethernet MAC.
• Support the PCS, PMA, and Physical Medium Dependent (PMD) sublayers defined
for the 10GBASE-R/KR and 40GBASE-R/KR protocols.
• Support up to the maximum transceiver data rate on any protocol that is 64/66-
bit encoded.
With KR FEC, the BER performance of the system can be improved.
Transcode Encoder
The KR forward error correction (KR FEC) transcode encoder block performs the
64B/66B to 65-bit transcoder function by generating the transcode bit. The transcode
bit is generated from a combination of 66 bits after the 64B/66B encoder which
consists of a 2-bit synchronization header (S0 and S1) and a 64-bit payload (D0, D1,
…, D63). To ensure a DC-balanced pattern, the transcode word is generated by
performing an XOR function on the second synchronization bit S1 and payload bit D8.
The transcode bit becomes the LSB of the 65-bit pattern output of the transcode
encoder.
Figure 244. Transcode Encoder
D63 ... D9 D8 ... D0 S1
S0
D63 ... D9 D8 ... D0 S1^D8
66-Bit Input
65-Bit Output
KR FEC Encoder
FEC (2112,2080) is an FEC code specified in Clause 74 of the IEEE 802.3 specification.
The code is a shortened cyclic code (2112, 2080). For each block of 2080 message
bits, another 32 parity checks are generated by the encoder to form a total of 2112
bits. The generator polynomial is:
g(x) = x
32
+ x
23
+ x
21
+ x
11
+ x
2
+1
KR FEC Scrambler
The KR FEC scrambler block performs scrambling based on the generation polynomial
x
58
+ x
39
+1, which is necessary for establishing FEC block synchronization in the
receiver and to ensure DC balance.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
470

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex