Intel Arria 10 User Manual

5. Arria 10 Transceiver PHY Architecture........................................................................ 447
5.1. Arria 10 PMA Architecture................................................................................... 447
5.1.1. Transmitter........................................................................................... 447
5.1.2. Receiver................................................................................................450
5.1.3. Loopback.............................................................................................. 460
5.2. Arria 10 Enhanced PCS Architecture.....................................................................461
5.2.1. Transmitter Datapath.............................................................................462
5.2.2. Receiver Datapath.................................................................................471
5.3. Arria 10 Standard PCS Architecture..................................................................... 479
5.3.1. Transmitter Datapath..............................................................................480
5.3.2. Receiver Datapath..................................................................................485
5.4. Arria 10 PCI Express Gen3 PCS Architecture......................................................... 495
5.4.1. Transmitter Datapath.............................................................................496
5.4.2. Receiver Datapath..................................................................................497
5.4.3. PIPE Interface........................................................................................498
5.5. Intel Arria 10 Transceiver PHY Architecture Revision History.....................................499
6. Reconfiguration Interface and Dynamic Reconfiguration .......................................... 502
6.1. Reconfiguring Channel and PLL Blocks...................................................................503
6.2. Interacting with the Reconfiguration Interface........................................................ 503
6.2.1. Reading from the Reconfiguration Interface............................................... 505
6.2.2. Writing to the Reconfiguration Interface.................................................... 505
6.3. Configuration Files............................................................................................. 506
6.4. Multiple Reconfiguration Profiles...........................................................................509
6.5. Embedded Reconfiguration Streamer.................................................................... 510
6.6. Arbitration.........................................................................................................512
6.7. Recommendations for Dynamic Reconfiguration......................................................515
6.8. Steps to Perform Dynamic Reconfiguration............................................................ 516
6.9. Direct Reconfiguration Flow................................................................................. 519
6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow..................................... 519
6.11. Reconfiguration Flow for Special Cases................................................................ 521
6.11.1. Switching Transmitter PLL ....................................................................521
6.11.2. Switching Reference Clocks....................................................................523
6.12. Changing PMA Analog Parameters......................................................................527
6.12.1. Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow................. 530
6.12.2. Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow.. 531
6.12.3. CTLE Settings in Triggered Adaptation Mode.............................................531
6.12.4. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow...533
6.13. Ports and Parameters........................................................................................535
6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks...................... 542
6.15. Embedded Debug Features................................................................................ 544
6.15.1. Altera Debug Master Endpoint................................................................ 544
6.15.2. Optional Reconfiguration Logic............................................................... 544
6.16. Using Data Pattern Generators and Checkers....................................................... 550
6.16.1. Using PRBS Data Pattern Generator and Checker..................................... 550
6.16.2. Using Pseudo Random Pattern Mode........................................................559
6.17. Timing Closure Recommendations...................................................................... 560
6.18. Unsupported Features....................................................................................... 563
6.19. Arria 10 Transceiver Register Map.......................................................................564
6.20. Reconfiguration Interface and Dynamic Revision History........................................ 564
Contents
Intel
®
Arria
®
10 Transceiver PHY User Guide
5

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex