Intel Arria 10 User Manual

In Arria 10 devices, there are two levels of arbitration:
• Reconfiguration interface arbitration with the PreSICE calibration engine
When you have control over the internal configuration bus, refer to the second
level of arbitration: Arbitration between multiple masters within the Native
PHY/PLL IPs.
For more details about arbitration between the reconfiguration interface and
PreSICE, refer to the Calibration chapter.
• Arbitration between multiple masters within the Native PHY/PLL IPs
Below are the feature blocks that can access the programmable registers:
— Embedded reconfiguration streamer (Available in the Native PHY and ATX PLL
IPs only)
— ADME
— User reconfiguration logic connected to the reconfiguration interface
When the internal configuration bus is not owned by the PreSICE, which feature
block has access depends on which of them are enabled.
These feature blocks arbitrate for control over the programmable space of each
transceiver channel/PLL. Each of these feature blocks can request access to the
programmable registers of a channel/PLL by performing a read or write operation
to that channel/PLL. For any of these feature blocks to be used, you must first
have control over the internal configuration bus. You must ensure that these
feature blocks have completed all the read/write operations before you return the
bus access to PreSICE.
The embedded reconfiguration streamer has the highest priority, followed by the
reconfiguration interface, followed by the ADME. When two feature blocks are
trying to access the same transceiver channel on the same clock cycle, the feature
block with the highest priority is given access. The only exception is when a lower-
priority feature block is in the middle of a read/write operation and a higher-
priority feature block tries to access the same channel. In this case, the higher
priority feature block is made to wait until the lower priority feature block has
finished the read/write operation.
Note: When you enable ADME in your design, you must
— connect an Avalon-MM master to the reconfiguration interface
—
OR connect the reconfig_clock,reconfig_reset signals and
ground the reconfig_write, reconfig_read, reconfig_address
and reconfig_writedata signals of the reconfiguration interface. If
the reconfiguration interface signals are not connected appropriately,
there is no clock or reset for the ADME, and the ADME does not function
as expected.
Related Information
• Steps to Perform Dynamic Reconfiguration on page 516
• Calibration on page 567
• Arria 10 Transceiver Register Map
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex