Intel Arria 10 - Page 513

Figure 271. Arria 10 Native PHY with Embedded Streamer
User
Reconfiguration
Logic
Streamer
ADME
Channel
Configuration
Registers
Avalon-MM
To/From
PreSICE
Interface
Optional Reconfiguration Logic
(Capability, Control and Status,
PRBS Soft Accumulators
Arria 10 Transceiver
Internal
Configuration
Bus
Arria 10 Native PHY
Debug Fabric
Host Link
Intel IP
Connectivity to channel reconfiguration registers
and optional soft registers
User Logic
Arbitration
Arbitration
Reconfiguration
Interface
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
513