Intel Arria 10 User Manual

Figure 276. Signals Available with Shared Native PHY Reconfiguration Interface
Native PHY IP Core
clk
reset
write
read
address
writedata
readdata
waitrequest
reconfig_clk
reconfig_reset
reconfig_write
reconfig_read
reconfig_address[11:0]
reconfig_writedata[31:0]
reconfig_readdata[31:0]
reconfig_waitrequest
Table 280. Reconfiguration Interface Ports with Shared Native PHY Reconfiguration
Interface
The reconfiguration interface ports when Share reconfiguration interface is enabled. <N> represents the
number of channels.
Port Name Direction Clock Domain Description
reconfig_clk
Input N/A Avalon clock. The clock frequency is 100-125
MHz.
reconfig_reset
Input
reconfig_clk
Resets the Avalon interface. Asynchronous to
assertion and synchronous to deassertion.
reconfig_write
Input
reconfig_clk
Write enable signal. Signal is active high.
reconfig_read
Input
reconfig_clk
Read enable signal. Signal is active high.
reconfig_address[log2<N>+9:0]
Input
reconfig_clk
Address bus. The lower 10 bits specify address
and the upper bits specify the channel.
reconfig_writedata[31:0]
Input
reconfig_clk
A 32-bit data write bus. Data to be written
into the address indicated by
reconfig_address.
reconfig_readdata[31:0]
Output
reconfig_clk
A 32-bit data read bus. Valid data is placed on
this bus after a read operation. Signal is valid
after reconfig_waitrequest goes high and
then low.
reconfig_waitrequest
Output
reconfig_clk
A one-bit signal that indicates the Avalon
interface is busy. Keep the Avalon command
asserted until the interface is ready to proceed
with the read/write transfer. The behavior of
this signal depends on whether the feature
Separate reconfig_waitrequest from the
status of AVMM arbitration with PreSICE
is enabled or not. For more details, refer to
the Arbitration section.
When
Share reconfiguration interface is off, the Native PHY IP core provides an
independent reconfiguration interface for each channel. For example, when a
reconfiguration interface is not shared for a four-channel Native PHY IP instance,
reconfig_address[9:0] corresponds to the reconfiguration address bus of logical
channel 0, reconfig_address[19:10] correspond to the reconfiguration address
bus of logical channel 1, reconfig_address[29:20] corresponds to the
reconfiguration address bus of logical channel 2, and reconfig_address[39:30]
correspond to the reconfiguration address bus of logical channel 3.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English