Intel Arria 10 User Manual

The following figure shows the signals available when the Native PHY is configured for
four channels and the Share reconfiguration interface option is not enabled.
Figure 277. Signals Available with Independent Native PHY Reconfiguration Interfaces
Native PHY IP Core
clk
reset
write
read
address
writedata
readdata
waitrequest
reconfig_clk[3:0]
reconfig_reset[3:0]
reconfig_write[3:0]
reconfig_read[3:0]
reconfig_address[39:0]
reconfig_writedata[127:0]
reconfig_readdata[127:0]
reconfig_waitrequest[3:0]
Table 281. Reconfiguration Interface Ports with Independent Native PHY
Reconfiguration Interfaces
The reconfiguration interface ports when Share reconfiguration interface is disabled. <N> represents the
number of channels.
Port Name Direction Clock Domain Description
reconfig_clk[N-1:0]
Input N/A Avalon clock for each channel. The clock
frequency is 100-125 MHz.
reconfig_reset[N-1:0]
Input
reconfig_clk
Resets the Avalon interface for each channel.
Asynchronous to assertion and synchronous to
deassertion.
reconfig_write[N-1:0]
Input
reconfig_clk
Write enable signal for each channel. Signal is
active high.
reconfig_read[N-1:0]
Input
reconfig_clk
Read enable signal for each channel. Signal is
active high.
reconfig_address[N*10-1:0]
Input
reconfig_clk
A 10-bit address bus for each channel.
reconfig_writedata[N*32-1:0]
Input
reconfig_clk
A 32-bit data write bus for each channel. Data
to be written into the address indicated by the
corresponding address field in
reconfig_address.
reconfig_readdata[N*32-1:0]
Output
reconfig_clk
A 32-bit data read bus for each channel. Valid
data is placed on this bus after a read
operation. Signal is valid after waitrequest
goes high and then low.
reconfig_waitrequest[N-1:0]
Output
reconfig_clk
A one-bit signal for each channel that
indicates the Avalon interface is busy. Keep
the Avalon command asserted until the
interface is ready to proceed with the read/
write transfer. The behavior of this signal
depends on whether the feature Separate
reconfig_waitrequest from the status of
AVMM arbitration with PreSICE is enabled
or not. For more details, refer to the
Arbitration section.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
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®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex