Intel Arria 10 User Manual

Table 282. Avalon Interface Parameters
The following parameters are available in the Dynamic Reconfiguration tab of the Transceiver Native PHY
and TX PLL parameter editors.
Note: The Native PHY and the PLL IP Parameter Editors give an error or warning message if any of
the parameter selections violate the legality checks.
Parameter Value Description
Enable dynamic reconfiguration On / Off Available in Native PHY and TX PLL IP parameter editors. Enables
the reconfiguration interface. Off by default. The reconfiguration
interface is exposed when this option is enabled.
Share reconfiguration interface On / Off Available in Native PHY IP parameter editor only. Enables you to
use a single reconfiguration interface to control all channels. Off
by default. If enabled, the uppermost bits of reconfig_address
identifies the active channel. The lower 10 bits specify the
reconfiguration address. Binary encoding is used to identify the
active channel (available only for Transceiver Native PHY). Enable
this option if the Native PHY is configured with more than one
channel.
Enable Altera Debug Master
Endpoint
On / Off Available in Native PHY and TX PLL IP parameter editors. When
enabled, the Altera Debug Master Endpoint (ADME) is instantiated
and has access to the Avalon-MM interface of the Native PHY. You
can access certain test and debug functions using System Console
with the ADME. Refer to the Embedded Debug Features section
for more details about ADME.
Separate reconfig_waitrequest
from the status of AVMM
arbitration with PreSICE
On / Off
When enabled, reconfig_waitrequest do not indicate the
status of AVMM arbitration with PreSICE. The AVMM arbitration
status is reflected in a soft status register bit. This feature
requires that the Enable control and status registers feature
under Optional Reconfiguration Logic be enabled. Refer to
Arbitration for more details on this feature. Refer to the
Calibration chapter for more details about calibration.
Enable capability registers On / Off Available in Native PHY and TX PLL IP parameter editors. Enables
capability registers. These registers provide high-level information
about the transceiver channel's /PLL's configuration.
Set user-defined IP identifier User-specified Available in Native PHY and TX PLL IP parameter editors. Sets a
user-defined numeric identifier that can be read from the
user_identifier offset when the capability registers are
enabled.
Enable control and status
registers
On / Off Available in Native PHY and TX PLL IP parameter editors. Enables
soft registers for reading status signals and writing control signals
on the PHY /PLL interface through the ADME or reconfiguration
interface.
Enable PRBS soft accumulators On / Off Available in Native PHY IP parameter editor only. Enables soft
logic to perform PRBS bit and error accumulation when using the
hard PRBS generator and checker.
Configuration file prefix User-specified Available in Native PHY and TX PLL IP parameter editors. Specifies
the file prefix used for generating configuration files. Use a unique
prefix for configuration files for each variant of the Native PHY
and PLL.
Generate SystemVerilog package
file
On / Off Available in Native PHY and TX PLL IP parameter editors. Creates
a SystemVerilog package file that contains the current
configuration data values for all reconfiguration addresses.
Disabled by default.
Generate C header file On / Off Available in Native PHY and TX PLL IP parameter editors. Creates
a C header file that contains the current configuration data values
for all reconfiguration addresses. Disabled by default.
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex