Intel Arria 10 User Manual

Parameter Value Description
Generate MIF (Memory Initialize
File)
On / Off Available in Native PHY and TX PLL IP parameter editors. Creates
a MIF file that contains the current configuration data values for
all reconfiguration addresses. Disabled by default.
Include PMA analog settings in
the configuration files
On / Off Available in Native PHY IP parameter editor only. When enabled,
the IP allows you to configure the analog settings for the PMA.
These settings are included in your generated configuration files.
Note: Even with this option enabled in the Native PHY IP
Parameter Editor, you must still specify QSF assignments
for your analog settings when compiling your static
design. The analog settings selected in the Native PHY IP
Parameter Editor are used only to include these settings
and their dependent settings in the selected configuration
files. For details about QSF assignments for the analog
settings, refer to the Analog Parameter Settings chapter.
Enable multiple reconfiguration
profiles
On / Off Available in Native PHY and ATX PLL IP parameter editors only.
Use the Parameter Editor to store multiple configurations. The
parameter settings for each profile are tabulated in the Parameter
Editor.
Enable embedded reconfiguration
streamer
On / Off Available in Native PHY and ATX PLL IP parameter editors only.
Embeds the reconfiguration streamer into the Native PHY/ATX PLL
IP cores and automates the dynamic reconfiguration process
between multiple predefined configuration profiles.
Generate reduced
reconfiguration files
On / Off Available in Native PHY and ATX PLLIP parameter editors only.
Enables the Native PHY and ATX PLL IP cores to generate
reconfiguration files that contain only the attributes that differ
between multiple profiles.
Number of reconfiguration
profiles
1 to 8 Available in Native PHY and ATX PLL IP parameter editors only.
Specifies the number of reconfiguration profiles to support when
multiple reconfiguration profiles are enabled.
Selected reconfiguration profile 0 to 7 Available in Native PHY and ATX PLL IP parameter editors only.
Selects which reconfiguration profile to store when you click
Store profile.
Store configuration to selected
profile
N/A Available in Native PHY and ATX PLL IP parameter editors only.
Stores the current Native PHY and ATX PLL parameter settings to
the profile specified by the Selected reconfiguration profile
parameter.
Load configuration from selected
profile
N/A Available in Native PHY and ATX PLL IP parameter editors only.
Loads the current Native PHY/ATX PLL IP with parameter settings
from the stored profile specified by the Selected
reconfiguration profile parameter.
Clear selected profile N/A Available in Native PHY and ATX PLL IP parameter editors only.
Clears the stored Native PHY/ATX PLL IP parameter settings for
the profile specified by the Selected reconfiguration profile
parameter. An empty profile defaults to the current parameter
settings of the Native PHY/ATX PLL. In other words, an empty
profile reflects the Native PHY/ATX PLL current parameter
settings.
Clear all profiles N/A Available in Native PHY and ATX PLL IP parameter editors only.
Clears the Native PHY/ATX PLL IP parameter settings for all the
profiles.
Refresh selected_profile N/A Available in Native PHY and ATX PLL IP parameter editors only.
Equivalent to clicking the Load configuration from selected
profile and Store configuration to selected profile buttons in
sequence. This operation loads the parameter settings from
stored profile specified by the Selected reconfiguration profile
parameter and then stores the parameters back to the profile.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
539

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex