Intel Arria 10 User Manual

Table 30. Standard PCS Parameters
Note: For detailed descriptions of the optional ports that you can enable or disable, refer to the
Standard PCS Ports on page 86 section.
Parameter Range Description
Standard PCS/PMA
interface width
8, 10, 16, 20 Specifies the data interface width between the Standard PCS and
the transceiver PMA.
FPGA fabric/Standard
TX PCS interface width
8, 10, 16, 20, 32, 40 Shows the FPGA fabric to TX PCS interface width. This value is
determined by the current configuration of individual blocks within
the Standard TX PCS datapath.
FPGA fabric/Standard
RX PCS interface width
8, 10, 16, 20, 32, 40 Shows the FPGA fabric to RX PCS interface width. This value is
determined by the current configuration of individual blocks within
the Standard RX PCS datapath.
Enable Standard PCS
low latency mode
On / Off Enables the low latency path for the Standard PCS. Some of the
functional blocks within the Standard PCS are bypassed to provide
the lowest latency. You cannot turn on this parameter while using
the Basic/Custom w/Rate Match (Standard PCS) specified for
Transceiver configuration rules.
Table 31. Standard PCS FIFO Parameters
Parameter Range Description
TX FIFO mode low_latency
register_fifo
fast_register
Specifies the Standard PCS TX FIFO mode. The following modes
are available:
• low_latency: This mode adds 2-3 cycles of latency to the TX
datapath.
• register_fifo: In this mode the FIFO is replaced by registers
to reduce the latency through the PCS. Use this mode for
protocols that require deterministic latency, such as CPRI.
• fast_register: This mode allows a higher maximum frequency
(f
MAX
) between the FPGA fabric and the TX PCS at the expense
of higher latency.
RX FIFO mode low_latency
register_fifo
The following modes are available:
• low_latency: This mode adds 2-3 cycles of latency to the RX
datapath.
• register_fifo: In this mode the FIFO is replaced by registers
to reduce the latency through the PCS. Use this mode for
protocols that require deterministic latency, such as CPRI or
1588.
Enable
tx_std_pcfifo_full port
On / Off
Enables the tx_std_pcfifo_full port. This signal indicates
when the standard TX phase compensation FIFO is full. This signal
is synchronous with tx_coreclkin.
Enable
tx_std_pcfifo_empty
port
On / Off
Enables the tx_std_pcfifo_empty port. This signal indicates
when the standard TX phase compensation FIFO is empty. This
signal is synchronous with tx_coreclkin.
Enable
rx_std_pcfifo_full port
On / Off
Enables the rx_std_pcfifo_full port. This signal indicates
when the standard RX phase compensation FIFO is full. This signal
is synchronous with rx_coreclkin.
Enable
rx_std_pcfifo_empty
port
On / Off
Enables the rx_std_pcfifo_empty port. This signal indicates
when the standard RX phase compensation FIFO is empty. This
signal is synchronous with rx_coreclkin.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
63

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex