Intel Arria 10 User Manual

Table 32. Byte Serializer and Deserializer Parameters
Parameter Range Description
Enable TX byte
serializer
Disabled
Serialize x2
Serialize x4
Specifies the TX byte serializer mode for the Standard PCS. The
transceiver architecture allows the Standard PCS to operate at
double or quadruple the data width of the PMA serializer. The byte
serializer allows the PCS to run at a lower internal clock frequency
to accommodate a wider range of FPGA interface widths.
Serialize x4 is only applicable for PCIe protocol implementation.
Enable RX byte
deserializer
Disabled
Deserialize x2
Deserialize x4
Specifies the mode for the RX byte deserializer in the Standard
PCS. The transceiver architecture allows the Standard PCS to
operate at double or quadruple the data width of the PMA
deserializer. The byte deserializer allows the PCS to run at a lower
internal clock frequency to accommodate a wider range of FPGA
interface widths. Deserialize x4 is only applicable for PCIe
protocol implementation.
Table 33. 8B/10B Encoder and Decoder Parameters
Parameter Range Description
Enable TX 8B/10B
encoder
On / Off When you turn on this option, the Standard PCS enables the TX
8B/10B encoder.
Enable TX 8B/10B
disparity control
On / Off When you turn on this option, the Standard PCS includes disparity
control for the 8B/10B encoder. You can force the disparity of the
8B/10B encoder using the tx_forcedisp control signal.
Enable RX 8B/10B
decoder
On / Off When you turn on this option, the Standard PCS includes the
8B/10B decoder.
Table 34. Rate Match FIFO Parameters
Parameter Range Description
RX rate match FIFO mode Disabled
Basic 10-bit PMA
width
Basic 20-bit PMA
width
GbE
PIPE
PIPE 0 ppm
Specifies the operation of the RX rate match FIFO in the Standard
PCS.
Rate Match FIFO in Basic (Single Width) Mode on page 306
Rate Match FIFO Basic (Double Width) Mode on page 308
Rate Match FIFO for GbE on page 117
Transceiver Channel Datapath for PIPE on page 230
RX rate match insert/
delete -ve pattern (hex)
User-specified 20 bit
pattern
Specifies the -ve (negative) disparity value for the RX rate match
FIFO as a hexadecimal string.
RX rate match insert/
delete +ve pattern (hex)
User-specified 20 bit
pattern
Specifies the +ve (positive) disparity value for the RX rate match
FIFO as a hexadecimal string.
Enable rx_std_rmfifo_full
port
On / Off
Enables the optional rx_std_rmfifo_full port.
Enable
rx_std_rmfifo_empty port
On / Off
Enables the rx_std_rmfifo_empty port.
PCI Express* Gen3 rate
match FIFO mode
Bypass
0 ppm
600 ppm
Specifies the PPM tolerance for the PCI Express Gen3 rate match
FIFO.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
64

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex