Intel Arria 10 User Manual

Table 35. Word Aligner and Bitslip Parameters
Parameter Range Description
Enable TX bitslip On / Off When you turn on this option, the PCS includes the bitslip
function. The outgoing TX data can be slipped by the
number of bits specified by the
tx_std_bitslipboundarysel control signal.
Enable tx_std_bitslipboundarysel
port
On / Off
Enables the tx_std_bitslipboundarysel control signal.
RX word aligner mode bitslip
manual (PLD
controlled)
synchronous state
machine
deterministic
latency
Specifies the RX word aligner mode for the Standard PCS.
The word aligned width depends on the PCS and PMA width,
and whether or not 8B/10B is enabled.
Refer to "Word Aligner" for more information.
RX word aligner pattern length 7, 8, 10, 16, 20,
32, 40
Specifies the length of the pattern the word aligner uses for
alignment.
Refer to "RX Word Aligner Pattern Length" table in "Word
Aligner". It shows the possible values of "Rx Word Aligner
Pattern Length" in all available word aligner modes.
RX word aligner pattern (hex) User-specified Specifies the word alignment pattern in hex.
Number of word alignment
patterns to achieve sync
0-255
Specifies the number of valid word alignment patterns that
must be received before the word aligner achieves
synchronization lock. The default is 3.
Number of invalid words to lose
sync
0-63
Specifies the number of invalid data codes or disparity
errors that must be received before the word aligner loses
synchronization. The default is 3.
Number of valid data words to
decrement error count
0-255
Specifies the number of valid data codes that must be
received to decrement the error counter. If the word aligner
receives enough valid data codes to decrement the error
count to 0, the word aligner returns to synchronization lock.
Enable fast sync status reporting
for deterministic Latency SM
On / Off
When enabled, the rx_syncstatus asserts high
immediately after the deserializer has completed slipping
the bits to achieve word alignment. When it is not selected,
rx_syncstatus asserts after the cycle slip operation is
complete and the word alignment pattern is detected by the
PCS (i.e. rx_patterndetect is asserted). This parameter
is only applicable when the selected protocol is CPRI (Auto).
Enable rx_std_wa_patternalign
port
On / Off
Enables the rx_std_wa_patternalign port. When the
word aligner is configured in manual mode and when this
signal is enabled, the word aligner aligns to next incoming
word alignment pattern.
Enable rx_std_wa_a1a2size port On / Off
Enables the optional rx_std_wa_a1a2size control input
port.
Enable
rx_std_bitslipboundarysel port
On / Off
Enables the optional rx_std_bitslipboundarysel status
output port.
Enable rx_bitslip port On / Off
Enables the rx_bitslip port. This port is shared between
the Standard PCS and Enhanced PCS.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
65

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex