Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 984
Dec 10, 2015
Figure 15-139. Flowchart for LIN Transmission
Note When LIN-bus start from sleep status only
Remark Default setting of the UART is complete, and the flow from the transmission enable status.
Starting LIN
communication
Transmitting wakeup signal frame
(
80H → TxD
0
)
UART 0 st op
(1 → ST00 bit)
End of LIN
communication
Trans mi tti ng
s
y
nc field
Operation of the hardware (reference
)
Ye s
TSF00 = 0?
No
Transmitting wakeup
signal frame
No t e
Waiting for completion
of transmission
8 bitsTxD0
Wakeup signal frame generation
Tra nsm i t da ta
Changing UART0 baud rate
(
zz → SDR
[
15:9
])
Changing baud rate
for BF
UART0 restar t
(1 → SS00 bit)
BF transmission
00 → TxD0
Yes
TSF00 = 0?
No
Waiting for
completion of BF
transmission
13-bit length TxD0
BF generation
Tra nsmi t da ta
UART0 stop
(
1 → ST00 bit
)
Changing UART
0
baud rate
(xx → SDR[15:9])
Retur n the baud rate
UART0 restart
(1 → SS00 bit
)
55H
TxD0
Sync field data generation
Waiting for completion of transmission (transmission
completed to the LIN bus)
Transmitting ID to
checksum
Transmitting sync field
55H → TxD0
Yes
TSF00 = 0?
No
Data → TxD0
Ye s
BFF00 = 0?
No
Yes
BFF00 = 0?
No
Yes
Completing all data
transmission?
No
Waiting for buffer
empty
Waiting for buffer empty
Waiting for transmission ID to checksum

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit