Renesas RL78 Series - CAN Transmit;Receive FIFO Receive Interrupt Status Register (CFISTS)

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1356
Dec 10, 2015
18.3.60 CAN Transmit/Receive FIFO Receive Interrupt Status Register (CFISTS)
Address CFISTS: F0363H
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — CF0IF
After Reset 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
7 to 1 — Reserved These bits are always read as 0. R
0 CF0IF CANi Transmit/Receive FIFO Buffer
k Receive Interrupt Request Status
Flag
0: No CANi transmit/receive FIFO buffer k receive
interrupt request is present.
1: A CANi transmit/receive FIFO buffer k receive
interrupt request is present.
R
The CFISTS register is cleared to H'00 in global reset mode.
• CF0IF Flag
The CF0IF flag is set to 1 when the CFRXIF flag in the CFSTSk register is set to 1 (a transmit/receive FIFO
receive interrupt request is present). When the CFRXIF flag is cleared to 0, the CF0IF flag is cleared to 0.