RL78/F13, F14 CHAPTER 7 TIMER RJ
R01UH0368EJ0210 Rev.2.10 559
Dec 10, 2015
7.4.4 Event Counter Mode
In this mode, the counter is decremented by an external event signal (count source) input to the TRJIO0 pin. Various
periods for counting events can be set by bits TIOGT0 and TIOGT1 in the TRJIOC0 register and the TRJISR0 register. In
addition, the filter function for the TRJIO0 input can be specified by bits TIPF0 and TIPF1 in the TRJIOC0 register.
Also, the output from the TRJO0 pin can be toggled even in event counter mode.
When event counter mode is used, see 7. 5. 5 Procedure for Setting Pins TRJO0 and TRJIO0.
Figure 7-14 shows the Operation Example in Event Counter Mode.
Caution The 20-pin products do not have TRJIO0 and TRJO0 pins. Thus, the event counter mode cannot be
used.
Figure 7-14. Operation Example 1 in Event Counter Mode
Bits TMOD2 to TMOD0
in TRJMR0 register
Event is counted at rising edge
Event counter mode is entered
Event input is started Event input is completed
Set to 0 by a program
Control bit in
TRJIOC0 register
TSTART bit
in TRJCR0 register
TRJIO0 pin
event input
Timer RJ0 counter
TUNDF bit in
TRJCR0 register
Counter initial value is set
010B
00H
FFFFH FFFEH FFFDH 0000H
FFFFH
FFFEH
IF bit in
INTC register
Acknowledgement of an interrupt request
Figure 7-15 shows an operation example for counting during the specified period in event counter mode (bits TlOGT1
and TlOGT0 in the TRJIO0 register are set to 01B or 10B).
To Next Page
Loading...
Need help?
General
