Renesas RL78 Series - Cani Transmit Buffer Register Pch (Tmdf1 P) (I = 0) (P = 0 to 3)

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1368
Dec 10, 2015
18.3.71 CANi Transmit Buffer Register pCH (TMDF1p) (i = 0) (p = 0 to 3)
Address TMDF10L: F060AH, TMDF10H: F060BH TMDF11L: F061AH, TMDF11H: F061BH
TMDF12L: F062AH, TMDF12H: F062BH TMDF13L: F063AH, TMDF13H: F063BH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TMDB3[7:0] TMDB2[7:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 8 TMDB3[7:0] Transmit Buffer Data Byte 3 Set transmit buffer data. R/W
7 to 0 TMDB2[7:0] Transmit Buffer Data Byte 2 R/W
Modify this register when the TMTRM bit in the corresponding TMSTSp register is set to 0 (no transmit request is
present). If this register is linked to any transmit/receive FIFO buffer, do not write data to this register.
This register can be read/written when the RPAGE bit in the GRWCR register is 1.