Renesas RL78 Series

RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 571
Dec 10, 2015
8.2.2 Clock Select Register (CKSEL)
This register is used to select the CPU clock (f
SUB/fIL) and the clocks for the timer RJ, timer RD, and clock
output/buzzer output. Together with the CMC register, the SELLOSC bit is used to set the operation mode of the
subsystem clock. For details, see Figure 5-3 Format of Clock Operation Mode Control Register (CMC).
Set the CKSEL register by a 1-bit or 8-bit memory manipulation instruction.
Writing to the CKSEL register is disabled when the GCSC bit of the IAWCTL register is set to 1.
Figure 8-3. Format of Clock Select Register (CKSEL)
Address: F02C4H After reset: 00H R/W
Symbol 7 6 5 4 3 <2> 1 <0>
CKSEL 0 0
0 0
0
TRD_
CKSEL
0
SELLOSC
Notes 5, 6
TRD_
CKSEL
Control of TRD clock selection
0 Selects fCLK or fMP
Note 1
.
1
Selects
fSL
Note 2
.
SELLOSC
Notes 5, 6
Control of sub/low-speed on-chip oscillator selection clock (f
SL) selection
0 Selects fSUB
Note 3
1 Selects fIL
Note 4
Notes 1. When FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and PLLDIV1 = 1
(f
PLL > 32 MHz) in the PLLCTL register, set the TRD_CKSEL bit to 0.
When FRQSEL4 = 1 in the user option byte (000C2H/020C2H) or PLLDIV1 = 1
(f
PLL > 32 MHz) in the PLLCTL register, the timer RD operating clock (fTRD) becomes fMP.
2. When f
SL is selected as the timer RD operating clock (fTRD), fSL should be selected as the
CPU clock
(set the CSS bit in the CKC register to 1).
3. When setting f
SUB as the CPU/peripheral hardware clock, first set the SELLOSC bit to 0 and
then set the CSS bit in the CKC register to 1.
4. When setting f
IL as the CPU/peripheral hardware clock, first set the SELLOSC bit to 1 and
then set the CSS bit in the CKC register to 1.
5. When the SELLOSC bit is set to 1, the low-speed on-chip oscillator operates.
6. When setting the CKSEL register in the 20-, 30-, or 32-pin products, set the SELLOSC bit to
1.