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Renesas RL78 Series - Cani Transmit;Receive FIFO Access Register Kbl (Cftsk) (I = 0) (K = 0)

Renesas RL78 Series
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RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1347
Dec 10, 2015
18.3.51 CANi Transmit/Receive FIFO Access Register kBL (CFTSk) (i = 0) (k = 0)
Address CFTS0L: F05E4H, CFTS0H: F05E5H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
CFTS[15:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 0 CFTS[15:0] Transmit/Receive FIFO Buffer
Timestamp Data
These bits are valid only when the CFM[1:0] value is
B'00 (receive mode).
The timestamp value of the received message can be
read.
R
This register can be read when the RPAGE bit in the GRWCR register is 1.
CFTS[15:0] Bits
These bits indicate the timestamp value of the message stored in the transmit/receive FIFO buffer.
These bits are valid when the CFM[1:0] value is B'00.

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