Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only)
R01UH0368EJ0210 Rev.2.10 769
Dec 10, 2015
13.3.4 D/A Converter Mode Register 2 (DAM2)
When the P80/ANO0 pin is in use to output analog signal from the D/A converter, this register is used to control the output
from the ANO0 pin. When setting bits 5 and 4 (CVRS1 and CVRS0) in the comparator I/O select register (CMPSEL) to 10B
(internal reference voltage (DAC output) is selected), set the ANO0EN bit in this register to 0 (analog output is disabled).
Set the DAM2 register by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-5. Format of D/A Converter Mode Register 2 (DAM2)
Address: F0227H After reset: 00H R/W
Symbol 7 6 <5> <4> 3 2 1 0
DAM2 0 0 0 0 0 0 0 ANO0EN
ANO0EN Analog output (ANO0) control R/W
0 Disables analog output (ANO0). R/W
1 Enables analog output (ANO0).

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit