RL78/F13, F14 CHAPTER 7 TIMER RJ
R01UH0368EJ0210 Rev.2.10 566
Dec 10, 2015
7.5.9 Functional Restriction in STOP Mode (Event Counter Mode Only)
When event counter mode operation is performed during STOP mode, the digital filter function cannot be used.
7.5.10 When Count is Forcibly Stopped by TSTOP Bit
After the counter is forcibly stopped by the TSTOP bit in the TRJCR0 register, do not access the following SFRs for one
cycle of the count source.
Registers TRJ0, TRJCR0, and TRJMR0
7.5.11 Digital Filter
When the digital filter is used, do not start timer operation for five cycles of the digital filter clock after setting bits TIPF1
and TIPF0.
Also, do not start timer operation for five cycles of the digital filter clock when the TEDGSEL bit in the TRJIOC register is
changed while the digital filter is used.
7.5.12 When Selecting fIL as Count Source
When selecting f
IL as the count source, set the WUTMMCK0 bit in the operation speed mode control register (OSMC) to
1. However, f
SUB cannot be selected as the count source for timer RJ when fSL (fIL) is selected as the count source for timer
RD or the output clock for clock output/buzzer output.
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