Renesas RL78 Series

RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 191
Dec 10, 2015
3.4.6 Register indirect addressing
[Function]
Register indirect addressing directly specifies the target addresses using the contents of the register pair specified
with the instruction word as an operand address.
[Operand format]
Identifier Description

[DE], [HL] (only the space from F0000H to FFFFFH is specifiable)

ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
Figure 3-53. Example of [DE], [HL]
Figure 3-54. Example of ES:[DE], ES:[HL]
FFFFFH
F0000H
rp(HL/DE)
Either pair of registers <1> specifies the target
location as an address in the 64-Kbyte area from
F0000H to FFFFFH.
[DE], [HL]
Target memory
Memory
<1> <1>
<1>
<1>
Specifies the
address in memory
Instruction code
OP-code
FFFFFH
00000H
X0000H
ES
OP-code rp(HL/DE)
The ES register <1> specifies a 64-Kbyte area within the
overall 1-Mbyte space as the four higher-order bits, X, of
the address range.
Either pair of registers <2> and the ES register <1> specify
the target location in the area from X0000H to XFFFFH.
ES: [DE], ES: [HL]
Target memory
Memory
<1>
Specifies the
address in memory
<2>
<2>
<2>
<1>
<1>
<1>
<2>
Specifies a
64-Kbyte area
Area from
X0000H to
XFFFFH
Instruction code