Renesas RL78 Series - Cani Transmit Buffer Interrupt Enable Register (TMIEC) (I = 0)

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1363
Dec 10, 2015
18.3.66 CANi Transmit Buffer Interrupt Enable Register (TMIEC) (i = 0)
Address TMIECL: F037AH, TMIECH: F037BH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — — — — — — TMIE3 TMIE2 TMIE1 TMIE0
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 4 — Reserved These bits are always read as 0. The write value
should always be 0.
R
3 TMIE3 CANi Transmit Buffer 3 Interrupt Enable 0: Transmit buffer interrupt is disabled.
1: Transmit buffer interrupt is enabled.
R/W
2 TMIE2 CANi Transmit Buffer 2 Interrupt Enable R/W
1 TMIE1 CANi Transmit Buffer 1 Interrupt Enable R/W
0 TMIE0 CANi Transmit Buffer 0 Interrupt Enable R/W
• TMIEp Bits (p = 0 to 3)
When any of these bits is set to 1 and the corresponding transmission has been completed, a transmit buffer
interrupt request is generated.
Modify these bits when the TMTRM flag in the corresponding TMSTSp register is 0 (no transmit request is
present).
Write 0 to bits corresponding to transmit buffers linked to transmit/receive FIFO buffers.