RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK
R01UH0368EJ0210 Rev.2.10 660
Dec 10, 2015
9.3.2 Operation speed mode control register (OSMC)
The RTCLPC bit can be used to reduce power consumption by stopping clock functions that are unnecessary. For
details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR.
Set the OSMC register by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-3. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
OSMC RTCLPC 0 0
WUTMMCK0
0 0 0 0
RTCLPC
Setting in STOP mode or HALT mode while subsystem/low-speed on-chip oscillator select
clock is selected as CPU clock
0
Enables supply of subsystem/low-speed on-chip oscillator select clock to peripheral
functions
(See Table 23-1 for peripheral functions whose operations are enabled.)
1
Stops supply of subsystem/low-speed on-chip oscillator select clock to peripheral functions
other than real-time clock.
To Next Page
Loading...
Need help?
General
