RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 451
Dec 10, 2015
6.3.5 Timer channel enable status register m (TEm)
The TEm register is used to enable or stop the timer operation of each channel.
Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel
stop register m (TTm). When a bit of the TSm register is set to 1, the corresponding bit of this register is set to 1. When a
bit of the TTm register is set to 1, the corresponding bit of this register is cleared to 0.
The TEm register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TEmL.
Reset signal generation clears this register to 0000H.
Figure 6-15. Format of Timer Channel Enable Status Register m (TEm)
Address: F01B0H, F01B1H (TE0), F01F0H, F01F1H (TE1) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEm 0 0 0 0
TEHm
3
0
TEHm
1
0
TEm
7
TEm
6
TEm
5
TEm
4
TEm
3
TEm
2
TEm
1
TEm
0
TEH
m3
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit
timer mode
0 Operation is stopped.
1 Operation is enabled.
TEH
m1
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit
timer mode
0 Operation is stopped.
1 Operation is enabled.
TEmn Indication of operation enable/stop status of channel n
0 Operation is stopped.
1 Operation is enabled.
This bit displays whether operation of the lower 8-bit timer for TEm1 and TEm3 is enabled or stopped when channel
1 or 3 is in the 8-bit timer mode.
Cautions 1. Be sure to clear bits 15 to 12, 10, and 8 to "0".
2. Be sure to clear TE1n (n = 7 to 4) to “0” in the Group B, C, and D products.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
2. TE1n is not provided in the Group A products.
TE17 to TE14 are not provided in the Group B, C, and D products.
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