Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only)
R01UH0368EJ0210 Rev.2.10 768
Dec 10, 2015
13.3.3 D/A Converter Mode Register (DAM)
This register controls the operation of the D/A converter.
Set the DAM register by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-4. Format of D/A Converter Mode Register (DAM)
Address: FFF36H After reset: 00H
Symbol 7 6 <5> <4> 3 2 1 0
DAM
  
DACE0
  
DAMD0
DACE0 D/A conversion operation control R/W
0 Stops D/A conversion operation. R/W
1 Enables D/A conversion operation.
DAMD0 D/A converter operation mode selection R/W
0 Normal mode R/W
1 Real-time output mode
When the D/A converter is not used, set the DACE0 bit to 0 (output disable) and set the DACS0 register to 00H to prevent
current from flowing into the R-2R resistor ladder to reduce unnecessary current consumption.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit