RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1306
Dec 10, 2015
18.3.15 CAN Global Transmit Interrupt Status Register (GTINTSTS)
Address GTINTSTSL: F0388H, GTINTSTSH: F0389H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — — — — — — THIF0 CFTIF0 TAIF0 TSIF0
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 4 — Reserved The read value is undefined. The write value should
always be 0.
R
3 THIF0 CANi Transmit History Interrupt
Status Flag
0: No transmit history interrupt request is present.
1: A transmit history interrupt request is present.
R
2 CFTIF0 CANi Transmit/Receive FIFO
Interrupt Status Flag
0: No transmit/receive FIFO transmit interrupt request is
present.
1: A transmit/receive FIFO transmit interrupt request is
present.
R
1 TAIF0 CANi Transmit Buffer Abort
Interrupt Status Flag
0: No transmit buffer abort interrupt request is present.
1: A transmit buffer abort interrupt request is present.
R
0 TSIF0 CANi Transmit Buffer Interrupt
Status Flag
0: No transmit buffer transmit complete interrupt request is
present.
1: A transmit buffer transmit complete interrupt request is
present.
R
All flags in the GTINTSTS register are cleared to 0 in global reset or channel reset mode.
• THIF0 Flag
The THIF0 flag is set to 1 when the THLIE bit in the THLCCi register is set to 1 (enabling interrupts) and the
THLIF flag in the THLSTSi register is set to 1 (interrupt request present).
This flag is cleared to 0 when the THLIF flag is set to 0. This flag is also cleared to 0 when the THLIE bit is set to
0.
• CFTIF0 Flag
The CFTIF0 flag is set to 1 when the CFTXIE bit in the CFCCLk register is set to 1 (enabling interrupts) and the
CFTXIF flag in the CFSTSk register is set to 1 (interrupt request present).
This flag is cleared to 0 when the CFTXIF flag is set to 0. This flag is also cleared to 0 when the CFTXIE bit is
set to 0.
• TAIF0 Flag
The TAIF0 flag is set to 1 when the TAIE bit in the CiCTRH register is set to 1 (enabling interrupts) and the
TMTRF[1:0] flag in the TMSTSp register is set to B'01 (transmit abort has been completed).
This flag is cleared to 0 when the TMTRF[1:0] flag, which indicates that the abortion of transmission has been
completed, is set to B'00.
• TSIF0 Flag
The TSIF0 flag is set to 1 when the TMIEp bit in the TMIEC register is set to 1 (enabling interrupts) and the
TMTRF[1:0] flag in the corresponding TMSTSp register is set to B’10 (transmission has been completed
(without transmit abort request) ) or B’11 (transmission has been completed (with transmit abort request)).
This flag is cleared to 0 when all TMTRF[1:0] flags that satisfy a condition for setting the TSIF0 flag to 1 are set
to B’00. This flag is also cleared to 0 when the TMIEp bit is set to 0.
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