Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA
R01UH0368EJ0210 Rev.2.10 1038
Dec 10, 2015
16.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers
(1) Setting transfer clock on master side
Transfer clock =
fMCK
IICWL0 + IICWH0 + fMCK (tR + tF)
At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows.
(The fractional parts of all setting values are rounded up.)
 When the fast mode
IICWL0 =
0.52
Transfer clock
 fMCK
IICWH0 = (
0.48
Transfer clock
 tR  tF)  fMCK
 When the normal mode
IICWL0 =
0.47
Transfer clock
 fMCK
IICWH0 = (
0.53
Transfer clock
 tR  tF)  fMCK
 When the fast mode plus
IICWL0 =
0.50
Transfer clock
 fMCK
IICWH0 = (
0.50
Transfer clock
 tR  tF)  fMCK
(2) Setting IICWL0 and IICWH0 registers on slave side
(The fractional parts of all setting values are truncated.)
 When the fast mode
IICWL0 = 1.3
 s  fMCK
IICWH0 = (1.2
 s  tR  tF)  fMCK
 When the normal mode
IICWL0 = 4.7
 s  fMCK
IICWH0 = (5.3
 s  tR  tF)  fMCK
 When the fast mode plus
IICWL0 = 0.50
 s  fMCK
IICWH0 = (0.50  s  tR  tF)  fMCK
(Cautions and Remarks are listed on the next page.)

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit