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Renesas RL78 Series User Manual

Renesas RL78 Series
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RL78/F13, F14 CHAPTER 12 A/D CONVERTER
R01UH0368EJ0210 Rev.2.10 739
Dec 10, 2015
12.6.4 Software trigger mode (scan mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by the
analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in
order, starting with that specified by scan 0.
<3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
<4> After A/D conversion of the four channels ends, the ADCS bit is automatically cleared to 0, and the system enters
the A/D conversion standby status.
<5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system
enters the A/D conversion standby status.
<8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D conversion
does not start even if a hardware trigger is input while in the A/D conversion standby status.
Figure 12-25. Example of Software Trigger Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
ADCE is set to 1.
<1>
The trigger
is not
acknowledged.
ADCS is set to 1 while
in the conversion
standby status.
<2>
Conversion
standby
Conversion
standby
Conversion
standby
Conversion
standby
Stop
status
Stop
status
Data 1
(ANI0)
Data 1
(ANI0)
Data 2
(ANI1)
Data 2
(ANI1)
Data 3
(ANI2)
Data 3
(ANI2)
Data 3
(ANI2)
Data 4
(ANI3)
Data 4
(ANI3)
Data 4
(ANI3)
Data 1
(ANI0)
Data 2
(ANI1)
Data 4
(ANI3)
Data 1
(ANI0)
Data 5
(ANI4)
Data 6
(ANI5)
Data 7
(ANI6)
Data 8
(ANI7)
Data 1
(ANI0)
Data 1
(ANI0)
Data 5
(ANI4)
Data 6
(ANI5)
Data 7
(ANI6)
Data 2
(ANI1)
Data 3
(ANI2)
Data 2
(ANI1)
Conversion is
interrupted and restarts.
Conversion is
interrupted and restarts.
<3>
ADCS is
automatically
cleared to
0 after
conversion
ends.
<4>
ADCS is overwritten
with 1 during A/D
conversion operation.
<5>
<2> <2><4>
Data 2
(ANI1)
Conversion is
interrupted.
ADCS is cleared
to 0 during A/D
conversion operation.
<7>
ADCE is cleared to 0.
<8>
The trigger
is not
acknowledged.
A/D conversion
ends.
<3>
The interrupt is generated four times. The interrupt is generated four times.
ADS is rewritten during
A/D conversion operation.
<6>
ANI0 to ANI3
ANI4 to ANI7
Data 1 (ANI0)

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Renesas RL78 Series Specifications

General IconGeneral
CoreRL78
CPU Clock SpeedUp to 32 MHz
Flash MemoryUp to 512 KB
RAMUp to 32 KB
Operating Voltage1.6 V to 5.5 V
Low Power ModesHALT, STOP, SNOOZE
CPU Architecture16-bit
Temperature Range-40°C to +85°C
PackageLQFP
Timers16-bit timers
Communication InterfacesUART, I2C, LIN
A/D Converter12-bit

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