Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA
R01UH0368EJ0210 Rev.2.10 1034
Dec 10, 2015
16.3.6 IICA low-level width setting register 0 (IICWL0)
This register is used to set the low-level width (t
LOW) of the SCLA0 pin signal that is output by serial interface IICA.
The IICWL0 register can be set by an 8-bit memory manipulation instruction.
Set the IICWL0 register while operation of I
2
C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) is 0).
Reset signal generation sets this register to FFH.
For details about setting the IICWL0 register, see 16.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers.
Figure 16-10. Format of IICA Low-Level Width Setting Register 0 (IICWL0)
Address: F0232H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
IICWL0
16.3.7 IICA high-level width setting register 0 (IICWH0)
This register is used to set the high-level width of the SCLA0 pin signal that is output by serial interface IICA.
The IICWH0 register can be set by an 8-bit memory manipulation instruction.
Set the IICWH0 register while operation of I
2
C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) is 0).
Reset signal generation sets this register to FFH.
Figure 16-11. Format of IICA High-Level Width Setting Register 0 (IICWH0)
Address: F0233H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
IICWH0
Remark For how to set the transfer clock by using the IICWL0 and IICWH0 registers, see 16.4.2 Setting
transfer clock by using IICWL0 and IICWH0 registers.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit