RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1355
Dec 10, 2015
18.3.59 CAN Receive FIFO Interrupt Status Register (RFISTS)
Address RFISTS: F0362H
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — RF1
IF
RF0
IF
After Reset 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
7 to 2 — Reserved These bits are always read as 0. R
1 RF1IF Receive FIFO Buffer 1 Interrupt
Request Status Flag
0: No receive FIFO buffer m interrupt request is present
(m = 0, 1).
1: A receive FIFO buffer m interrupt request is present.
R
0 RF0IF Receive FIFO Buffer 0 Interrupt
Request Status Flag
R
The RFISTS register is cleared to H'00 in global reset mode.
• RFmIF Flag
The RFmIF flag is set to 1 when the RFIF flag in the RFSTSm register is set to 1 (a receive FIFO interrupt
request is present). When the RFIF flag is cleared to 0, the RFmIF flag is cleared to 0.
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