RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 399
Dec 10, 2015
5.4.3 High-Speed On-Chip Oscillator
The high-speed on-chip oscillator is incorporated in the RL78/F13 and RL78/F14. The frequency can be selected from
among 64, 48, 32, 24, 16, 12, 8, 4, or 1 MHz by using the user option byte (000C2H/020C2H). When 64 MHz or 48 MHz is
selected, the frequency obtained by dividing the selected clock by 2 by the f
MP clock division register (MDIV) is supplied as
the CPU clock after a reset release. Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control
register (CSC).
The high-speed on-chip oscillator automatically starts oscillating after reset release.
5.4.4 PLL Circuit
The PLL circuit is incorporated in the RL78/F13 and RL78/F14. Operation of the PLL circuit can be controlled by bit 0
(PLLON) of the PLL control register (PLLCTL).
5.4.5 Low-Speed On-Chip Oscillator
The low-speed on-chip oscillator which can be used for the CPU/peripheral hardware clock is incorporated in the
RL78/F13 and RL78/F14.
5.4.6 WDT-Dedicated Low-Speed On-Chip Oscillator
The WDT-dedicated low-speed on-chip oscillator is incorporated in the RL78/F13 and RL78/F14.
The WDT-dedicated low-speed on-chip oscillator clock is used as the watchdog timer clock. This clock cannot be used
as the CPU clock.
The WDT-dedicated low-speed on-chip oscillator operates when bit 4 (WDTON) of the user option byte
(000C0H/020C0H) is set to 1. The WDT-dedicated low-speed on-chip oscillator continues oscillating while the watchdog
timer is operating. The WDT-dedicated low-speed on-chip oscillator does not stop while the watchdog timer is operating
even though the program goes out of control.
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