RL78/F13, F14 CHAPTER 24 RESET FUNCTION
R01UH0368EJ0210 Rev.2.10 1541
Dec 10, 2015
CHAPTER 24 RESET FUNCTION
The following seven operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit
(4) Internal reset by comparison of supply voltage of the voltage detector (LVD) and detection voltage
(5) Internal reset by execution of illegal instruction
Note
(6) Internal reset in response to the clock monitor detecting that oscillation of the main clock has stopped
(7) Internal reset by illegal-memory access
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is
generated.
When a low level is input to the RESET pin, the watchdog timer detects an overflow, a voltage is detected on the POR
and LVD circuits, an illegal instruction is executed
Note
, the clock monitor detects that oscillation of the main clock has stopped,
or memory is accessed illegally, the device is reset and the hardware is set to the status shown in Table 24-1.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is
input to the RESET pin and program execution is started with the high-speed on-chip oscillator clock after reset processing.
A reset by the watchdog timer is automatically released, and program execution starts using the high-speed on-chip oscillator
clock (see Figures 24-2 to 24-4) after reset processing. Reset by POR and LVD circuit supply voltage detection is
automatically released when VDD VPOR or VDD VLVD is detected after the reset, and program execution starts using the
high-speed on-chip oscillator clock (see CHAPTER 25 POWER-ON-RESET CIRCUIT and CHAPTER 26 VOLTAGE
DETECTOR) after reset processing.
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Cautions 1. For an external reset, input the low level to the RESET pin for at least 10 s.
When an external reset is applied while the power supply voltage is rising, the period over which
the voltage is below the range of operating voltage (V
DD < 2.7V) is not included in the 10 s. However,
continuing the input of a low level before release from the power-on reset state does not create a
problem.
2. During reset input, the X1 clock, XT1 clock, high-speed on-chip oscillator clock, and low-speed on-
chip oscillator clock stop oscillating. External main system clock input and external subsystem
clock input become invalid.
3. When reset is effected, port pin P130 is set to low-level output and other port pins become high-
impedance, because each SFR and 2nd SFR are initialized.
Remark V
POR: POR power supply rise detection voltage
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